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po wer ma nage m ent and m ulti ma rk et high - p erf or manc e dr m o s 6 mm x 6 mm x 0.8 mm iqfn dat a she et revision 2.5 , 2013 - 01 - 07 td a21 220
edition 2013 - 01 - 07 published by infineon technologies ag 81726 munich, germany ? 2013 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologi es hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non - infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and c onditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in qu estion, please contact the nearest infineon technologies office. infineon technologies components may be used in life - support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life - support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sust ain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
tda21220 dat a sheet 3 revision 2.5 , 2013 - 01 - 07 revision history page or item su bjects (major changes since previous revision) revision 2.5 , 2013 - 01 - 07 u pdated page 4 trademarks of infineon technologies ag aurix?, bluemoon ?, c166?, canpak?, cipos?, cipurse?, comneon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my - d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pro - sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x - gold?, x - pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent technologies, amba?, arm?, multi - ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetoo th sig inc. cat - iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epcos? of epcos ag. flexgo? of microsoft corporation. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorp orated. iec? of commission electrotechnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nxp. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwa ve? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. tea klite? of ceva, inc. tektronix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorporated. vxworks?, wind river? of wind river systems , inc. zetex? of diodes zetex limited . last trademarks update 2010 - 10 - 26
tda21220 applications dat a sheet 4 revision 2.5 , 2013 - 01 - 07 1 applications ? desktop and server vr11.x and vr12 .x buck - converter ? network and telecom processor vr ? single phase and multiphase pol ? cpu/gpu regulation in notebook, desktop graphics cards, ddr memory, graphic memory ? high power density voltage regulator modules (vrm). 2 features ? compliant to intel ? vr1 2 .x driver and mosfets module (drmos) for desktop/server applications ? for synchronous bu ck step down voltage applications ? maximum average current of 50 a ? power mosfets rated 25 v for safe operation under all conditions ? extremely fast switching technology for improved performance at high switching frequencie s (> 1 mhz) ? remote driver disable function ? switch modulation (smod#) of low side mosfet ? includes bootstrap diode ? undervoltage lockout ? shoot through protection ? +5 v h igh side and l ow s ide mosfets driving voltage ? compatible to standard +3.3 v pwm controller integrated circuits ? t ri - state pwm input functionality ? small package: iqfn40 (6 x 6 x 0.8 mm3) ? rohs compliant table 1 product identification part number temp range package marking tda21220 - 25 to 125 ? figure 1 picture of the p roduct
tda21220 d escription dat a sheet 5 revision 2.5 , 2013 - 01 - 07 3 description 3.1 pinout figure 2 pinout, n umbering and n ame of p ins (transparent top view) note: signals marked with # at the end are active low signals. table 2 i/o signals pin no. name pin type buffer type function 1 smod# i +3.3 v logic low side gate disable when smod# is low the gl is off 6 gh o analog high side gate signal monitoring of h igh s ide mosfet gate 7 phase i analog switch node (reference for boot voltage) i nternally connected to vswh pin, c onnect to boot capacitor 4 boot i analog bootstrap voltage pin connect to boot capacitor 15, 29 to 35, vswh pad vswh o analog switch node output high current output switching node 36 gl o analog low side gate signal monitoring of l ow s ide mosfet gate 39 disb# i +3.3 v logic disable signal (active low) connect to gnd to disable the ic. 40 pwm i +3.3 v logic pwm drive logic input the t ri - state pwm input is compatible with 3.3 v. vswh vin 1 2 3 4 5 6 7 8 9 10 11 40 20 21 31 30 cgnd vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd pwm vswh vswh vswh vswh vswh gl cgnd nc disb# pwm vswh vswh vswh vswh vswh gl cgnd nc disb# 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 39 38 37 36 35 34 33 32 vin vin nc phase gh cgnd boot vdrv vcin smod# vin vin nc phase gh cgnd boot vdrv vcin smod# pgnd pgnd pgnd vswh vswh pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd vswh vswh pgnd pgnd pgnd pgnd pgnd
tda21220 description dat a sheet 6 revision 2.5 , 2013 - 01 - 07 table 3 power supply pin no. name pin type buffer type function 2 vcin power C logic supply voltage 5 v bias voltage for the internal logic 3 vdrv power C fet gate supply voltage high and l ow s ide mosfets gate drive supply 9 to 14, vin pad vin power C input voltage supply of the drain of the h igh s ide mosfet table 4 ground pins pin no. name pin type buffer type function 5, 37, cgnd pad cgnd gnd C control signal ground should be connected to pgnd externally 16 to 28 pgnd gnd C power ground all these pins must be connected to the power gnd plane through multiple low inductance vias. table 5 not connected pin no. name pin type buffer type function 8, 38 nc C C no internal connection leave pin floating or tie to gnd.
tda21220 description dat a sheet 7 revision 2.5 , 2013 - 01 - 07 3.2 general description the infineon tda21220 is a multichip module that incorporates infineons premier mosfet technology for a single high side and a single low side mosfet coupled with a robust, high performance, high switching frequency gate driver in a single 40 pin qfn package. the optimized gate timing allows for significant light load efficiency improvements over discrete solutions. state of the art mosfet technology pr ovides exceptional full load performance . wh en combined with the infineons f amily of digital multi phase c ontrollers, the tda21220 forms a complete core - voltage regulator solution for advanced micro and graphics processors as well as point - of - load applicat ions. the tda21220 is pin to pin compatible and compliant with the intel 6x6 drmos specification. the device package height is only 0.8 mm, and is an excellent choice for applications with critical height limitations. figure 3 simplif ied block diagram s m o d # d i s b # p g n d v s w h h s d r i v e r l s d r i v e r u v l o l s l o g i c i n p u t l o g i c t r i - s t a t e p w m v c i n v d r v c g n d g l b o o t v i n d r i v e r i c p h a s e l s m o s f e t v d r v v d r v l e v e l s h i f t e r h s l o g i c g h 5 0 0 k c g n d 7 k 1 c g n d 1 6 k 5 v c i n 6 0 0 k c g n d 4 0 0 k v c i n 5 0 0 k 5 0 0 k + + - - h s m o s f e t s h o o t t h r o u g h p r o t e c t i o n u n i t
tda21220 electrical specification dat a sheet 8 revision 2.5 , 2013 - 01 - 07 4 electrical s pecification 4.1 absolute maximum ratings note: t a mbient = 25c stresses above those listed in table 6 absolute maximum ratings may cause permanent damage to the device. these are absolute stress ratings only and operation of the device is not implied or recommended at these or any other co nditions in excess of those given in the operational sections of this specification. exposure to the absolute maximum ratings for extended periods may adversely affect the operation and reliability of the device. table 6 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. frequency of the pwm input f sw C C C out C C C in (dc) - 0.30 C C cin (dc) - 0.30 C C drv (dc) - 0.30 C C swh (dc) - 1 C C swh (ac) - 10 1 C C phase (dc) - 1 C C phase (ac) - 10 C C boot (dc) - 0.3 C C boot (ac) - 1 1 C C boot - phase (dc) - 1 C C smod# (dc) - 0.3 C C disb 2 - 0.3 C C pwm 2 - 0.3 C C jmax - 40 C ? C stg - 5 5 C C note: all rated voltages are relative to voltages on the cgnd and pgnd pins unless otherwise specified. 1 ac is limited to 10 ns 2 latch up class ii - level b (jedec 78). please refer to quality report for details.
tda21220 electrical specification dat a sheet 9 revision 2.5 , 2013 - 01 - 07 4.2 thermal characteristics table 7 thermal characteristics parameter symbol values unit note / test condition min. typ. max. thermal resistance, junction - soldering point 1 js C 5 C k/w C thermal resistance, junction - top of package jtop C 20 C C 4.3 recommended operating conditions and electrical characteristics note: v drv = v cin = 5 v, t a mbient = 25c (conditions for table 8 through table 12 unless otherwise specified) table 8 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. input voltage v in 5 C 16 v C mosfet driver voltage v drv 4.5 5 5.5 C logic supply voltage v cin 4.5 5 5.5 v cin rising,3.3v to 3.9v: dv cin /dt > 300v/s junction temperature t jop - 25 C 125 c C table 9 voltage supply and biasing current parameter symbol values unit note / test condition min. typ. max. driver current i vdrv_300khz C C sw = 300 khz i vdrv_pwml C C a vcin_pwml C C vcin_o C C vc in + i vd rv C C uvlo_r 2.9 3.5 3.9 v v cin rising,3.3v to 3.9v: dv cin /dt > 300v/s uvlo falling v uvlo_f 2.5 3.1 3.3 vcin falling 1 the junction - soldering point is referred to the vswh bottom exposed pad.
tda21220 electrical specification dat a sheet 10 revision 2.5 , 2013 - 01 - 07 table 10 logic inputs and threshold parameter symbol values unit note / test condition min. typ. max. disb# input low v disb_l 0.7 1.1 1.3 v v disb falling input high v disb_h 1.9 2.1 2.4 v disb rising sink current i disb C C a disb = 1 v smod# input low v smod#_l 0.7 1.1 1.3 v v smod# falling input high v smod#_h 1.9 2.1 2.4 v smod# rising open voltage v smod#_o C C C smod# C C a smod# = 1 v pwm input low v pwm_l C C pwm falling input high v pwm_h 2.4 C C pwm rising input resistance r in - pwm 3 5 7 k ? pwm = 1 v open voltage v pwm_o C C pwm_o tristate shutdown window 1 v pwm_s 1.2 C C table 11 timing characteristics parameter symbol values unit note / test condition min. typ. max. tri - state to gl/gh rising delay t _pts C C C C C C C C C C C C C C C C C C C C C C 1 maximum voltage range for tri - state
tda21220 electrical specification dat a sheet 11 revision 2.5 , 2013 - 01 - 07 table 12 recommended operation timing parameter symbol min. typ. max. unit test conditions smod# rising to pwm rising edge set - up time t_surll - 20 - ns smod# falling to pwm falling edge hold time t_hfll - 20 - time t_surll is a recommended maximum time between smod# disabling and pwm going high to prevent the ls - mosfet from turning on prior to its immediate turn - off. time t_hfll is a recommended maximum time between pwm falling and smod# enabling to prevent the ls - mosfet from turning on prior to its immediate turn - off.
tda21220 theory of operation dat a sheet 12 revision 2.5 , 2013 - 01 - 07 5 theory of operation the tda21220 incorporates a high performance gate driver, one high side power mosfet and on e low side power mosfet in a single 40 lead qfn package. the advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance.this module is ideal for use in syn chronous bu ck regulators . the power mosfets are optimized for 5 v gate drive enabling excellent high load and light load efficiency. the gate driver is a robust high - performance driver rated at the switching nod e for dc voltages ranging from - 1 v to +25 v . t he power density for transmitted power of this approach is approximately 4 0 w within a 36 mm 2 area. 5.1 driver characteristics the gate driver of the tda21220 has two voltage inputs, vcin and vdrv. vcin is the logic supply for the driver. vdrv sets the driving voltage for the high side and low side mosfets . the reference for the gate driver control circuit (vcin) is cgnd. to decouple the sensitive control circuitry (logic supply) from a noisy environment a ceramic capacitor must be placed between vcin and cgnd close to the pins. vdrv also needs to be decoupled using a ceramic capacitor (mlcc) between vdrv and pgnd in close proximity to the pins. pgnd serves as reference for the power circuitry including the driver output stage . referring to figure 3 ( block diagram ) , vcin is internally connected to the uvlo (undervoltage - lockout) circuit and for vcin voltages less than required for proper circuit operation will pro vide shut - down. vdrv supplies the floating high side drive C consisting of an active boot circuit - and the low - side drive circuit. a second uvlo circuitry, sensing the boot voltage level, is implemented to prevent false gh turn on during insufficient powe r supply level condition (boot c ap charging/discharging sequence). during an undervoltage event gh and gl will both be driven low . in addition, a 50 0 k ? pull - down resistor is placed from gate to source at both fets . figure 4 internal o utput s ignal from uvlo u nit v cin h l uvlo_f v uvlo_r uvlo output logic level shutdown enable
tda21220 theory of operation dat a sheet 13 revision 2.5 , 2013 - 01 - 07 5.2 inputs to the internal control circuits the pwm is the control input to the ic from an external pwm controller and is compatible with 3.3 v. the pwm input has t ri - state functionality. when the voltage remains in the specified pwm - shutdown - window for at least the pwm - shutdown - holdoff time ( t _ gl tsshd , t _ gh tsshd ) the operation will be suspended by keeping both mosfet gate outputs low. once left open, the pin is held internal lyat a level of v pwm_o = 1.5 v level . table 13 pwm pin functionality pwm logic level driver output low gl= high, gh = low high gl = low, gh = high open (left floating, or h igh impedance) gl = low, gh = low once a logic high spike has been captured the pwm logic will prolongate the logic high state to the minimum of t_ on_min_pwm . equivalently, once a logic low spike has been captured the pwm logic will prolongate the logic low state to the minimum of t_ o ff_ min_pwm . using a wide range vcin power supply (from 4.5 v to 5.5 v) causes a shifting in the threshold voltages for the following parameters: v pmw_o , v pwm_h , v pwm_l , v pwm_ s . the typical behavior of these thresholds over vcin voltage variation is shown in the following graph: figure 5 variation of pwm levels versus vcin logic supply voltage
tda21220 theory of operation dat a sheet 14 revision 2.5 , 2013 - 01 - 07 vcin requires a minimum dv/dt of 300 v/s in the vicinity of the uvlo threshold to prevent the driver logic from emitting any gate drive glitches. the disb# is an active low signal. when pulled low, the power stage is disabled. the disable pin is being held low internally during the thermal shut down condition. table 14 disb# pin functionality disb# logic level driver output low shutdown : gl = gh = low high enable : gl = gh = active open (left floating, or h igh impedance) shutdown : gl = gh = low the smod# fea ture is provided to disable the low - side mosfet during active operation. when synchronized with the pwm signal, smod# can be used to improve light load efficiency by sav ing the gate charge loss of the low - side mosfet. once left open, the pin is internally fixed to v smod# _o = 3 v level. table 15 smod# pin functionality smod# logic level driver output low shutdown : gl = low , gh = pwm high enable : gl = gh = active open (left floating, or high impedance) enable : gl = gh = active 5.3 shoot through protection the tda21220 driver includes gate drive functionality to protect against shoot through. in order to protect the p ower stage from overlap, both h igh s ide and l ow s ide mosfets being on at the same time, the adaptive control circuitry monitors the voltage at the vswh p in. when the pwm signal transitions to low , the h igh s ide mosfet will begin to turn off after the propagation dela y time t_pdlu. when v gs of the h igh s ide mosfet is discharged below 1 v ( a threshold below which the h igh s ide mosfet is off) , a secondary del ay t _pdhl is initiated . after that delay the l ow s ide mosfet turns on regardless of the state of the vswh pin. it ensures that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each swi tching cycle. see figure 9 for more detail. gh and gl are monitoring pins to check the internal gate drive signals.
tda21220 theory of operation dat a sheet 15 revision 2.5 , 2013 - 01 - 07 5.4 safe operating area the maximum load current versus the temperature of the pcb (below the device) is given below: figure 6 safe operating area (condition: v in = 12 v, v out = 1.2 v, f sw = 362 khz)
tda21220 application dat a sheet 16 revision 2.5 , 2013 - 01 - 07 6 application 6.1 implementation figure 7 pin interconnection outline (transparent top view) note: 1. pin phase is internally connected to vswh node 2. it is recommended to place a rc filter between vcin and vdrv as shown. 3. during power - up and down sequences, the pwm signal must be either low or tri - state (open voltage), but never high, in order to avoid uncontrolled output voltage. v s w h v i n 1 2 3 4 5 6 7 8 9 1 0 1 1 4 0 2 0 2 1 3 1 3 0 c g n d v i n v s w h p g n d p w m v s w h g l c g n d n c d i s b # 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 v i n n c p h a s e g h c g n d b o o t v d r v v c i n s m o d # v s w h p g n d 1 f 2 x 2 2 f 2 x 1 f 1 x 0 . 1 f c i n v i n c b o o t + 5 v v o u t l 1 f + 5 v 1 r d i s b # - p u ( 5 v . . . 2 0 v ) c o u t
tda21220 application dat a sheet 17 revision 2.5 , 2013 - 01 - 07 6.2 typical application figure 8 four - p hase v oltage r egulator - t ypical application (s implified s chematic)
tda21220 gate driver timing diagram dat a sheet 18 revision 2.5 , 2013 - 01 - 07 7 gate driver timing diagram figure 9 adaptive gate driver timing diagram figure 10 disb# timing diagram disb# gh / gl t_pdl _ disb v disb#_l t_pdh _ disb v disb#_h pwm gl gh 1 v tri - state v pwm_l t_pdhl t_gltsshd t_pdl l t_pdh u t_pdl u v pwm_l t_ghtssd t_pts t_pts vswh note : vswh during entering/exit ing tri - state behaves dependen d on inductor current. 1 v 1 v (threshold for gl enable) v pwm_h v pwm _h v pwm_h
tda21220 gate driver timing diagram dat a sheet 19 revision 2.5 , 2013 - 01 - 07 figure 11 smod# timing diagram figure 12 smod# timing diagram vswh pwm gl smod disabled smod active dcm ccm ccm smod# t_pdfll smod disabled t_surll gh v smod#_l v smod#_h pwm smod# disabled gl smod# t_pdfll smod# enabled gh t_pdrhl t_surll t_hfll smod# enabled smod# enabled
tda21220 performance curves C typical data dat a sheet 20 revision 2.5 , 2013 - 01 - 07 8 performance curves C typical data 8.1 efficiency and power loss versus v out operating conditions (un less otherwise specified): vin = +12 v, vcin = vdrv = +5 v, vout = 0.8 v to 1.6 v, f sw = 362 khz, 210 nh inductor (c ooper - fpi1108, dcr (typ . ) = 0.29 m ) t a = 25 c, load line = 0 m, airflow = 100 lfm, no heatsink. efficiency and p ower l oss reported herein include only tda21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. figure 13 efficiency vs. output current , vout as parameter
tda21220 performance curves C typical data dat a sheet 21 revision 2.5 , 2013 - 01 - 07 figure 14 power l oss vs. output current , vout as parameter
tda21220 performance curves C typical data dat a sheet 22 revision 2.5 , 2013 - 01 - 07 8.2 efficiency and power loss versus v in operating conditions (unless otherwise specified): vin = +10/12/14 v, vcin = vdrv = +5 v, vout = 1.2 v, f sw = 362 khz, 210 nh inductor (cooper - fpi1108, dcr (typ) = 0.29 m ) t a = 25 c, load line = 0 m, airflow = 100 lfm, no heatsink. efficiency and p ower l oss reported herein include only tda21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. figure 15 efficiency vs. output current , vin as parameter
tda21220 performance curves C typical data dat a sheet 23 revision 2.5 , 2013 - 01 - 07 figure 16 power l oss vs. output current with vin as parameter
tda21220 performance curves C typical data dat a sheet 24 revision 2.5 , 2013 - 01 - 07 8.3 efficiency and power loss versus switching frequency operating conditions (unless otherwise specified): vin = +12 v, vcin = vdrv= +5 v, vout = 1.2 v, f sw = 296 khz to f sw = 592 khz, 210 nh inductor (cooper - fpi1108, dcr (typ) =0.29 m ) t a = 25 c, load line = 0 m , airflow = 100 lfm, no heatsink. efficiency a nd p ower l oss reported herein include only tda21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. figure 17 efficiency vs. output current, switching frequency as parameter
tda21220 perf ormance curves C typical data dat a sheet 25 revision 2.5 , 2013 - 01 - 07 figure 18 power l oss vs. output current, switching frequency as parameter
tda21220 performance curves C typical data dat a sheet 26 revision 2.5 , 2013 - 01 - 07 8.4 driver current versus switching frequency operating conditions (unless otherwise specified): vin = +12 v, vcin = vdrv = + 5 v, vout = 1.2 v, from f sw = 296 khz to f sw = 592 khz, 210 nh indu ctor (cooper - fpi11 08, dcr (typ) = 0.29 m ) t a = 25 c, load line = 0 m, airflow = 100 lfm, no heatsink. efficiency and p ower l oss reported herein includes only tda21220 losses. data are taken after thermal equilibrium (~ 10 min for each current step) with unit in temperature chamber. figure 19 driver current v s . switching frequency
tda21220 mechanical drawing dat a sheet 27 revision 2.5 , 2013 - 01 - 07 9 mechanical drawing figure 20 mechanical dimensions f7 n e f1 f2 f3 f4 f5 l f6 millimeters a dim min e max inches min max 2.5 scale z8b00137095 revision issue date european projection 02 17-04-2009 0 5mm 0 2.5 document no. d a e 3 e 2 e l b d2 d3 k 1 k 2 footprint c d2 b c d d2 d3 e e2 e3 k1 k2 z z 0.75 0.85 0.030 0.033 0.18 0.10 5.90 1.90 4.30 5.90 1.40 2.30 0.63 0.11 0.28 0.30 6.10 2.10 4.50 6.10 1.60 2.50 0.83 0.31 0.007 0.004 0.232 0.075 0.169 0.232 0.055 0.091 0.025 0.004 0.011 0.012 0.240 0.083 0.177 0.240 0.063 0.098 0.033 0.012 0.30 40 0.50 40 0.012 0.020 1 11 21 31 0.50 0.020 4.40 0.173 2.40 0.094 2.00 0.079 1.50 0.059 0.25 0.010 0.70 0.028 0.40 0.016 f 2 f 4 f 5 f3 f1 f6 f7 a1 a 1 0.00 0.05 0.000 0.002
tda21220 mechanical drawing dat a sheet 28 revision 2.5 , 2013 - 01 - 07 figure 21 footprint and solder stencil recommendations attention: the recommended stencil height is 120 m. assembly recommendations can be found in this document: recommendations for printed circuit board assembly of infineon pg - iqfn packages figure 22 marking definitio n pad "a" (40x) pad size solder mask solder paste 6.60 6.60 1.20 1.20 1.48 0.99 0.20 typ solder paste (2x) solder paste (6x) pad "b" (2x) pad "c" 0.70 x 0.25 0.78 x 0.35 0.65 x 0.20 2.00 x 1.50 2.05 x 1.55 0.80 x 1.30 4.40 x 2.40 4.45 x 2.45 1.26 x 1.00 a b c pad size solder mask pad size solder mask pin 1 marking manufacturer type code h = rohs compliant + halogen-free g = green product / rohs compliant production lot code 12345678 xx
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